1. Field of the Invention
The present invention relates to methods and apparatus for acquisition of signal information from a circuit using a particle-beam prober, particularly an electron-beam prober.
2. The Prior Art
FIG. 1 shows a prior art electron beam test probe system 10 having an electron beam test probe 12, a circuit exerciser 14, and a data processing system 16 with display terminal 18. Circuit exerciser 14 is a conventional integrated circuit tester which can repeatedly apply a pattern of test vectors to a specimen circuit 26 over a bus 24 (such as a model 9000 tester available from Schlumberger Technologies, Inc. of San Jose, Calif.). The specimen circuit 26 (device under test, or DUT) is placed in test probe 12 so that samples of voltages on nodes of the DUT can be acquired as the test vector pattern is applied. Processing system 16 communicates with circuit exercizer 14, and with test probe 12 over bus 22, to specify the test vector pattern and timing of the sample points relative to the test vector pattern. System 10 is controlled by operator commands through display terminal 18.
Test probe 12 has a SEM column with beam blanker for directing electron-beam pulses at a DUT node of interest in a mode of operation much like that of a sampling oscilloscope. The waveform on one or more nodes of interest can be sampled and an image produced as the DUT is exercised. The images can be qualitative (e.g., logic state maps for digital circuit debug) or, with a secondary-electron energy analyzer, quantitative (e.g., analog signal waveforms).
For each point of the waveform image, the electron beam is pulsed at a specific time during application of the test vector pattern to the DUT. Each time the beam is pulsed, the potential on a node of the DUT is sampled. As one sample is not statistically accurate enough for accurate measurement of the potential, samples acquired over many repetitions of the pattern are averaged. The pulses are coordinated with the test vector pattern by a trigger generator circuit under control of data processing system 16.
FIG. 2 is a partial functional diagram of an electron beam test probe system configured to acquire waveform images. Timing controller 30 receives a trigger signal from tester 14 and supplies beam-pulse timing signals to the electron-optics of test probe 12. Potential-sample signals from test probe 12 are digitized by analog-to-digital converter (ADC) 32 under control of a timing signal synchronized with the beam pulse timing signals, and supplied to one input of an arithmetic logic unit (ALU) 34. A second input of ALU 34 receives data from a data buffer 36. ALU 34 returns the weighted sum of the two input values to data buffer 36 under control of data buffer address controller 38. Controller 38 communicates with timing controller 30, and with processor 40 via communication interface 42. Controller 38 keeps track of which data relates to which point in the waveform when such data is stored in data buffer 36 so that the data can be composed as a waveform image for display.
The desired waveform image is to be composed of values at n sample points during the test vector pattern. Each sample point is assigned an address in data buffer 36. The timing diagram of FIG. 3 shows a trigger signal pulse 340 from tester 14 which causes timing control circuit 30 to supply a beam pulse 342 to test probe 12 at delay t.sub.1 following trigger pulse 340. When a succeeding trigger pulse 344 is produced by tester 14, timing control circuit 30 produces a beam pulse 346 at delay t.sub.1 after trigger pulse 344. Each trigger pulse (340, 344, etc.) typically represents one repetition of the test vector pattern applied to the DUT. Samples are repeatedly acquired at a delay t.sub.1 following the trigger pulses until enough pulses are acquired and averaged to give a meaningful measurement at that sample point. The process is repeated for a second sample point at delay t.sub.2, for a third sample point at delay t.sub.3, and so on through an nth sample point at delay t.sub.n. This may require thousands of test vector pattern repetitions for each sample point in the waveform and hundreds of thousands of repetitions to acquire the waveform image.
Acquisition time can be reduced as shown in FIG. 4 by acquiring multiple samples during each test vector pattern repetition. At time t.sub.1 following trigger pulse 450, beam pulse 452 is produced. Further beam pulses 454, 456, etc., are produced at an interval m.multidot.dt following pulse 452, where m is an integer and dt represents the time interval between points in the desired waveform. In this example, m=4, so the waveform is sampled at one fourth (1/m) of the sample points with each test pattern repetition. When enough samples have been averaged for these sample points, the beam pulses are retarded by a time dt such that the first beam pulse 460 follows a trigger pulse by a time t.sub.2 =t.sub.1 +dt. Samples are acquired and averaged for an additional one fourth of the sample points with each test pattern repetition. The process is repeated for a delay t.sub.3 =t.sub.2 +dt and a delay t.sub.4 =t.sub.3 +dt to acquire and average samples for the remaining sample points of the waveform. Implementation is further described in U.S. Pat. No. 5,144,225, the content of which is incorporated herein by this reference.
FIG. 5 schematically illustrates prior-an acquisition of the waveform on a DUT 500. As primary electron beam 505 is directed at the DUT, secondary electrons 510 are detected by a detector 515 which supplies a secondary electron current Isec. Current Isec varies non-linearly with changes in the surface potential Vdut on DUT 500. A feedback loop comprising of a difference amplifier 520, reference current source 535, gated integrator 525 and filter mesh 530 is employed to linearize the relationship between Isec and Vdut. Difference amplifier 520 generates an error signal Iint whose amplitude depends on the difference between Isec and the reference current Iref from constant current source 535. The error signal is passed through controlled gate 540 to capacitor 545 and amplifier 550 of integrator 525. Integrator 525 supplies a voltage Vfilter to filter mesh 530. The number of electrons with sufficient energy to overcome the potential barrier of the filter mesh is governed by the difference between DUT voltage Vdut and filter voltage Vfilter. When Vdut changes, the feedback loop acts to make the same number of electrons overcome the potential barrier (i.e., keep Isec constant) by varying Vfilter. This condition is achieved if the change in filter voltage is the same as the change in the DUT voltage. That is, the filter voltage tracks (with a fixed offset) variations in Vdut. Gate 540 is closed once during each beam-pulse interval.
Assume for example that Vdut=0 V, Vfilter=-7 V and the loop is settled (Isec=Iref) at a given sample point. Let Vdut be +5 V at the next sample point. Vfilter will go from being -7 V with respect to Vdut to being -12 V with respect to Vdut, and fewer number of electrons will have sufficient energy to overcome the filter potential barrier. Isec will thus be smaller than Iref, and this imbalance will cause an error current Iint to flow out of the integrator. Error-current Iint reduces the charge stored in the integrator's capacitor, and the integrator output becomes more positive. This change in Vfilter lowers the potential barrier for the secondary electrons, thereby increasing Isec, which will in turn Vfilter more positive. The loop will eventually settle when Vfilter =-2 V. That is, when Vdut changes from 0 V to +5 V, Vfilter changes from -7 V to -2 V (a +5 V change) to settle the loop.
The loop settling time depends on the magnitude of the change in Vfilter needed to settle the loop. Since, I=C * (.DELTA.V/.DELTA.T), the loop settling time can be written as .DELTA.T=(C * AV)/I. Isec depends on the width of the sampling-beam pulse. Typically, Iint=Isec-Iref is a very small current and is insufficient to change the filter voltage appreciably. Multiple sampling-beam pulses are therefore needed to drive the filter voltage to the final value. Thus, the smaller the sampling-beam pulse-width, the more sampling-beam pulses are needed per measurement. For example, for a 1 nanosecond pulse-width, 1000 sampling-beam pulses may be needed to settle the loop, while 3500 sampling-beam pulses may be needed for a 200 ps pulse-width. The current needed to settle the loop, I=Iint* J, where J is the number of sampling-beam pulses per measurement. The time needed to make a voltage measurement (loop settling time) increases for a larger change in Vfilter from one measurement to the next, and decreases for a smaller change in Vfilter from one measurement to the next. The loop settling time increases when a larger capacitor is used and decreases when a smaller capacitor is used. Further, the loop settling time decreases when fewer sampling-beam pulses are used per measurement and increases when more sampling-beam pulses are used per measurement. A large capacitor and a large number of sampling-beam pulses per measurement allow for a low-noise but slower measurement of the DUT voltage. A faster and noisier measurement can be achieved by using a smaller capacitor and fewer sampling-beam pulses per measurement. A typical approach is to compromise between low noise and fast loop settling.
Measurement of Vdut as described above is typically repeated at a plurality of delays (t1, t2, . . . , tm) from the trigger to obtain a waveform image or sweep. Such measurements are typically noisy. The noise is usually random in nature and can be reduced by obtaining many sweeps and averaging the results. For example, N sweeps may be made, each sweep consisting of M measurements. The N samples at delay t1 may be averaged and the result displayed as the voltage measurement at delay t1. This is repeated for the measurements at delays t2, t3, . . . , tm.
There are two ways to obtain a sweep: linear and random. FIG. 3 is an example of the linear mode, in which the delay between the trigger and successive sample points is linearly incremented by a fixed interval. FIG. 6 illustrates the succession of sample points 1 through 9 in a linear-mode sampling scheme. The DUT voltage Vdut is measured at the first delay from the trigger to sample point (sample point 1), then Vdut is measured at a second delay from the trigger to the sample point (sample point (2), etc. The change in Vdut from one sample point to the next sample point is usually not large. That is, Vdut at sample point 2 is not much different from Vdut at the previous sample point (1) or the successive sample point 3. For a given sampling-beam pulse-width and capacitor size, linear sampling requires fewer sampling-beam pulses per measurement to settle the loop than does random sampling. For this reason, linear sampling mode is the faster of the two modes.
Random mode sampling is typically used to measure DUT voltage changes for passivated devices or when measuring voltage changes on conductors buried under a dielectric layer. FIGS. 7-9 show why. In FIG. 7, conductor 700 is buried under a dielectric layer 710. A pulsed electron-beam 720 produces secondary electrons 730. When the actual waveform on conductor 700 is switched between high and low voltages as in FIG. 8A, the measured waveform is distorted as in FIG. 8B due to capacitive coupling between conductor 700 and the surface of dielectric 710. FIG. 9 shows an equivalent circuit in which voltage source 900 represents conductor 700, capacitor 910 represents dielectric 710, switch 920 represents (when closed) an electron-beam pulse, and resistor 940 represents a path for leakage of charge from dielectric 710. Because many samples are needed for a useful measurement at a given sample point, the sampling rate is kept as high as possible to minimize waveform acquisition time. But since dielectric 710 charges up each time sampling beam 720 hits the DUT, a high sampling rate using the linear sampling mode does not allow time for the charge to dissipate.
In random mode sampling, the delay between the trigger and the successive sample points is changed in a pseudo-random or random manner. FIG. 10 illustrates, with sample points 1 through 9 arranged in pseudo-random or random order. For example, a first sample is taken at some delay from trigger to sample point (sample point 1), then a second sample is taken at a different delay from trigger to sample point (sample point 2), etc. Since the delay between the trigger and successive sample points is varied in a random or pseudo-random manner, there is a high probability that the change in Vdut between successive samples can be equal to the maximum change in Vdut (for example, Vdut changes by the maximum amount between sample points 1 and 2 in FIG. 10). Since the filter voltage Vfilter has to track the change in Vdut, the loop settling time is large in random sampling mode. If the capacitor used is the same as in linear mode, then more sampling-beam pulses are needed per measurement (longer loop settling time) for random mode. If a smaller capacitor is used without changing the number of sampling-beam pulses per measurement, noise increases. Typically, a combination of a smaller capacitor and an increased number of samples is used for random mode. For example, for a 1 nanosecond beam pulse width, the number of samples is increased from 1000 in linear mode to 2000 in random mode, and the capacitor is decreased from 2200 pF in linear mode to 1000 pF in random mode. In this example, random mode takes approximately 5 times longer than linear mode to reach a desired signal-to-noise ratio.
U.S. Pat. No. 5,210,487 shows (in FIG. 11 of the patent) a scheme in which the voltage of the filter grid Vfilter is produced by convening a measured-voltage signal to an analog voltage and summing this analog voltage with an offset voltage Voffset which sets the operating point of the filter grid. U.S. Pat. No. 5,210,487 shows (in FIG. 13 of the patent) a scheme in which the voltage of the filter grid Vfilter is produced by summing the measured-voltage signal from the integrator with an offset voltage Voffset which sets the operating point of the filter grid.
U.S. Pat. No. 5,144,225 shows (in FIG. 12 of the patent) a scheme in which a sampling circuit is operates as multiple loops in parallel. Each time a measurement is taken at a given delay following the trigger signal, the filter voltage is set by the output of a DAC based on a stored rolling average of previous voltage measurements at that delay following the trigger signal. The integration loop in this scheme has a built-in delay due to the delays involved in digitizing signal from the e-beam column of the prober, storing the digitized value in memory and applying the stored value to the filter at the next measurement at that delay. That is, real-time feedback control is not possible with this scheme. Also, the same measurement parameters are used for successive measurements at each sample point.